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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xr16v564/564d 2.25v to 3.6v quad uart with 32-byte fifo may 2007 rev. 1.0.1 general description the xr16v564 1 (v564) is an enhanced quad universal asynchronous re ceiver and transmitter (uart) with 32 bytes of transmit and receive fifos, programmable transmit and receive fifo trigger levels, automatic hardware and software flow control, and data rates of up to 16 mbps at 4x sampling rate. each uart has a set of registers that provide the user with operating status and control, receiver error indications, and modem seri al interface controls. an internal loopback capa bility allows onboard diagnostics. the v564 is available in a 48-pin qfn, 64-pin lqfp, 68-pin plcc and 80-pin lqfp packages. the 64-pin and 80-pin packages only offer the 16 mode interface, but the 48 and 68 pin packages offer an additional 68 mode interface which allows easy integration with motorola processors. the xr16v564iv (64-pin) offers three state interrupt output while the xr16v564 div provides continuous interrupt output. the xr16v564 is compatible with the industry standard st16c554 and st16c654/ 654d. n ote : 1 covered by u.s. patent #5,649,122. features ? pin-to-pin compatible with st16c454, st16c554, ti?s tl16c754b a nd philip?s sc16c754b ? intel or motorola data bus interface select ? four independent uart channels register set compatible to 16c550 data rates of up to 16 mbps 32 byte transmit fifo 32 byte receive fifo with error tags 4 selectable tx and rx fifo trigger levels automatic hardware (rts/cts) flow control automatic software (xon/xoff) flow control programmable xon/xoff characters wireless infrared (irda 1.0) encoder/decoder full modem interface ? 2.25v to 3.6v supply operation ? sleep mode with automatic wake-up ? crystal oscillator or external clock input applications ? portable appliances ? telecommunication network routers ? ethernet network routers ? cellular data devices ? factory automation and process controls f igure 1. xr16v564 b lock d iagram xtal1 xtal2 crystal osc/buffer data bus interface uart channel a 32 byte tx fifo 32 byte rx fifo brg ir endec tx & rx uart regs 2.25v to 3.6v vcc gnd 564 blk txb, rxb, dtrb#, dsrb#, rtsb#, ctsb#, cdb#, rib# uart channel b (same as channel a) a2:a0 d7:d0 csa# 16/68# csb# inta intb iow # ior# reset intsel txrdy# a-d rxrdy# a-d uart channel c (same as channel a) txa, rxa, dtra#, dsra#, rtsa#, ctsa#, cda#, ria# txc, rxc, dtrc#, dsrc#, rtsc#, ctsc#, cdc#, ric# uart channel d (same as channel a) txd, rxd, dtrd#, dsrd#, rtsd#, ctsd#, cdd#, rid# csc# csd# intc intd clksel * 5 volt tolerant inputs (except xtal1 input)
xr16v564/564d 2 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 f igure 2. p in o ut a ssignment f or 68- pin plcc p ackages i n 16 and 68 m ode and 64- pin lqfp p ackages 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 63 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 dsra# ctsa# dtra# vcc rtsa# inta csa# txa iow# txb csb# intb rtsb# gnd dtrb# ctsb# dsrb# cdb# rib# rxb clksel 16/68# a2 a1 a0 xtal1 xtal2 reset rxrdy# txrdy# gnd rxc ric# cdc# dsrd# ctsd# dtrd# gnd rtsd# intd csd# txd ior# txc csc# intc rtsc# vcc dtrc# ctsc# dsrc# cda# ria# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 intsel vcc rxd rid# cdd# xr16v564 68-pin plcc intel mode (16/68# pin connected to vcc) 9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 63 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 dsra# ctsa# dtra# vcc rtsa# irq# cs# txa r/w# txb a3 n.c. rtsb# gnd dtrb# ctsb# dsrb# cdb# rib# rxb clksel 16/68# a2 a1 a0 xtal1 xtal2 reset rxrdy# txrdy# gnd rxc ric# cdc# dsrd# ctsd# dtrd# gnd rtsd# n.c. n.c. txd n.c. txc a4 n.c. rtsc# vcc dtrc# ctsc# dsrc# cda# ria# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 gnd vcc rxd rid# cdd# xr16v564 68-pin plcc motorola mode (16/68# pin connected to gnd) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 dsra# ctsa# dtra# vcc rtsa# inta csa# txa iow# txb csb# intb rtsb# gnd dtrb# ctsb# dsrb# cdb# rib# rxb clksel a2 a1 a0 xtal1 xtal2 reset gnd rxc ric# cdc# dsrc# dsrd# ctsd# dtrd# gnd rtsd# intd csd# txd ior# txc csc# intc rtsc# vcc dtrc# ctsc# cda# ria# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 vcc rxd rid# cdd# xr16v564 64-pin tqfp intel mode only
xr16v564/564d 3 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo f igure 3. p in o ut a ssignment f or 48- pin qfn p ackage and 80- pin lqfp p ackage 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 ctsa# vcc rtsa# inta csa# txa iow# txb intb csb# rtsb# ctsb# rxb 16/68# a2 a1 a0 xtal1 xtal2 reset gnd rxc ctsc# vcc rxd ctsd# gnd rtsd# intd csd# txd ior# txc csc# intc rtsc# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 intsel vcc xr16v564 48-pin qfn xr16v564 80-pin lqfp intel mode only 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 n.c. cda# ria# rxa gnd d7 d6 d5 d4 d3 d2 d1 d0 intsel vcc rxd rid# cdd# n.c. n.c. n.c. dsrd# ctsd# dtrd# gnd rtsd# intd csd# txd ior# txc csc# intc rtsc# vcc dtrc# ctsc# dsrc# n.c. n.c. n.c. n.c. cdb# rib# rxb clksel n.c. a2 a1 a0 xtal1 xtal2 reset rxrdy# txrdy# gnd rxc ric# cdc# n.c. nc nc dsra# ctsa# dtra# vcc rtsa# inta csa# txa iow# txb csb# intb rtsb# gnd dtrb# ctsb# dsrb# nc
xr16v564/564d 4 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 pin descriptions ordering information p art n umber p ackage o perating t emperature r ange d evice s tatus xr16v564ij 68-lead plcc -40c to +85c active xr16v564iv 64-lead lqfp -40c to +85c active XR16V564DIV 64-lead lqfp -40c to +85c active xr16v564il 48-pin qfn -40c to +85c active xr16v564iv80 80-lead lqfp -40c to +85c active pin description n ame 48-qfn p in # 64-lqfp p in # 68-plcc p in # 80-lqfp p in # t ype d escription data bus interface a2 a1 a0 15 16 17 22 23 24 32 33 34 28 29 30 i address data lines [2:0]. these 3 address lines select one of the internal registers in uart channel a-d dur - ing a data bus transaction. d7 d6 d5 d4 d3 d2 d1 d0 46 45 44 43 42 41 40 39 60 59 58 57 56 55 54 53 5 4 3 2 1 68 67 66 75 74 73 72 71 70 69 68 i/o data bus lines [7:0] (bidirectional). ior# (vcc) 29 40 52 51 i when 16/68# pin is high, the intel bus interface is selected and this input becomes read strobe (active low). the falling edge instigates an internal read cycle and retrieves the data byte from an internal register pointed by the address lines [a2:a0], puts the data byte on the data bus to allow the host processor to read it on the rising edge. when 16/68# pin is low, the motorola bus interface is selected and this input is not used and should be con - nected to vcc. iow# (r/w#) 7 9 18 11 i when 16/68# pin is high, it selects intel bus interface and this input becomes write strobe (active low). the falling edge instigat es the internal write cycle and the rising edge transfers the data byte on the data bus to an internal register pointed by the address lines. when 16/68# pin is low, the motorola bus interface is selected and this input becomes read (logic 1) and write (low) signal. csa# (cs#) 5 7 16 9 i when 16/68# pin is high, this input is chip select a (active low) to enable channel a in the device. when 16/68# pin is low, this input becomes the chip select (active low) for t he motorola bus interface.
xr16v564/564d 5 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo csb# (a3) 9 11 20 13 i when 16/68# pin is high, this input is chip select b (active low) to enable channel b in the device. when 16/68# pin is low, this input becomes address line a3 which is used for channel selection in the motorola bus interface. csc# (a4) 27 38 50 49 i when 16/68# pin is high, this input is chip select c (active low) to enable channel c in the device. when 16/68# pin is low, this input becomes address line a4 which is used for channel selection in the motorola bus interface. csd# (vcc) 31 42 54 53 i when 16/68# pin is high, this input is chip select d (active low) to enable channel d in the device. when 16/68# pin is low, this input is not used and should be connected vcc. inta (irq#) 4 6 15 8 o (od) when 16/68# pin is high for intel bus interface, this ouput becomes channel a interrupt output. the output state is defined by the user and through the software setting of mcr[3]. inta is set to the active mode when mcr[3] is set to a logic 1. inta is set to the three state mode when mcr[3] is set to a logic 0 (default). see mcr[3]. when 16/68# pin is low for motorola bus interface, this output becomes device interrupt output (active low, open drain). an external pull-up resistor is required for proper operation. intb intc intd (n.c.) 10 26 32 12 37 43 21 49 55 14 48 54 o when 16/68# pin is high for intel bus interface, these ouputs become the interrupt outputs for channels b, c, and d. the output state is defined by the user through the software setting of mcr[3]. the interrupt outputs are set to the active mode when mcr[3] is set to a logic 1 and are set to the three state mode when mcr[3] is set to a logic 0 (default). see mcr[3]. when 16/68# pin is low for motorola bus interface, these outputs are unused and will stay at logic zero level. leave these outputs unconnected. txrdy# - - 39 35 o transmitter ready (active low). this output is a logi - cally anded status of txrdy# a-d. see ta b l e 5 . if this output is unused , leave it unconnected. rxrdy# - - 38 34 o receiver ready (active low). this output is a logically anded status of rxrdy# a-d. see ta b l e 5 . if this output is unused, l eave it unconnected. pin description n ame 48-qfn p in # 64-lqfp p in # 68-plcc p in # 80-lqfp p in # t ype d escription
xr16v564/564d 6 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 intsel 38 - 65 67 i interrupt select (active high, input with internal pull- down). when 16/68# pin is high for intel bus interface, this pin can be used in conjunction with mcr bit-3 to enable or disable the int a-d pins or override mcr bit-3 and enable the interrupt outputs. interrupt out - puts are enabled continuously when this pin is high. mcr bit-3 enables and disables the interrupt output pins. in this mode, mcr bit-3 is set to a logic 1 to enable the continuous output. see mcr bit-3 descrip - tion for full detail. this pin must be low in the motor - ola bus interface mode. for the 64 pin packages, this pin is bonded to vcc internally in the xr16v564d so the int outputs operate in the continuous interrupt mode. this pin is bonded to gnd internally in the xr16v564 and therefore requires setting mcr bit-3 for enabling the interrupt output pins. modem or serial i/o interface txa txb txc txd 6 8 28 30 8 10 39 41 17 19 51 53 10 12 50 52 o uart channels a-d transmit data and infrared trans - mit data. standard transmit and receive interface is enabled when mcr[6] = 0. in this mode, the tx signal will be a high during reset, or idle (no data). infrared irda transmit and receive interface is enabled when mcr[6] = 1. in the infrared mode, the inactive state (no data) for the infrared en coder/decoder interface is a logic 0. rxa rxb rxc rxd 48 13 22 36 62 20 29 51 7 29 41 63 77 25 37 65 i uart channel a-d receive data or infrared receive data. normal receive data input must idle high. rtsa# rtsb# rtsc# rtsd# 3 11 25 33 5 13 36 44 14 22 48 56 7 15 47 55 o uart channels a-d request-to-send (active low) or general purpose output. this output must be asserted prior to using auto rts flow control, see efr[6], mcr[1], and ier[6]. also see figure 11 . if these outputs are not used, l eave them unconnected. ctsa# ctsb# ctsc# ctsd# 1 12 23 35 2 16 33 47 11 25 45 59 4 18 44 58 i uart channels a-d clear-to-send (active low) or gen - eral purpose input. it can be used for auto cts flow control, see efr[7], and ier[7]. also see figure 11 . these inputs should be connected to vcc when not used. dtra# dtrb# dtrc# dtrd# - - - - 3 15 34 46 12 24 46 58 5 17 45 57 o uart channels a-d data-terminal-ready (active low) or general purpose output. if these outputs are not used, leave them unconnected. dsra# dsrb# dsrc# dsrd# - - - - 1 17 32 48 10 26 44 60 3 19 43 59 i uart channels a-d data-set-ready (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. pin description n ame 48-qfn p in # 64-lqfp p in # 68-plcc p in # 80-lqfp p in # t ype d escription
xr16v564/564d 7 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo cda# cdb# cdc# cdd# - - - - 64 18 31 49 9 27 43 61 79 23 39 63 i uart channels a-d carrier-detect (active low) or general purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. ria# rib# ric# rid# - - - - 63 19 30 50 8 28 42 62 78 24 38 64 i uart channels a-d ring-indicator (active low) or gen - eral purpose input. this input should be connected to vcc when not used. this input has no effect on the uart. ancillary signals xtal1 18 25 35 31 i crystal or external clock input. caution: this input is not 5v tolerant. xtal2 19 26 36 32 o crystal or buffered clock output. 16/68# 14 - 31 - i intel or motorola bus select (input with internal pull- up). when 16/68# pin is high, 16 or intel mode, the device will operate in the intel bus type of interface. when 16/68# pin is low, 68 or motorola mode, the device will operate in the motorola bus type of inter - face. motorola bus interface is not available on the 64 pin package. clksel - 21 30 26 i baud-rate-generator input clock prescaler select for channels a-d. this input is only sampled during power up or a reset. connect to vcc for divide by 1 (default) and gnd for divide by 4. mcr[7] can override the state of this pin following a reset or initialization. see mcr bit-7 and figure 6 in the baud rate generator section. reset (reset#) 20 27 37 33 i when 16/68# pin is high for intel bus interface, this input becomes the reset pin (active high). in this case, a 40 ns minimum high pulse on this pin will reset the internal registers and all outputs. the uart transmitter output will be held high, the receiver input will be ignored and outputs are reset during reset period ( ta b l e 17 ). when 16/68# pin is at low for motorola bus interface, this input becomes reset# pin (active low). this pin functions similarly, but instead of a high pulse, a 40 ns minimum low pulse will reset the internal registers and outputs. motorola bus interface is not available on the 64 pin package. vcc 2, 24, 37 4, 35, 52 13, 47, 64 6, 46, 66 pwr 2.25v to 3.6v power supply. all inputs, except xtal1, are 5v tolerant. gnd 21, 47 14, 28, 45, 61 6, 23, 40, 57 16, 36, 56, 76 pwr power supply common, ground. pin description n ame 48-qfn p in # 64-lqfp p in # 68-plcc p in # 80-lqfp p in # t ype d escription
xr16v564/564d 8 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 pin type: i=input, o=output, i/o= input/output, od=output open drain. gnd center pad n/a n/a n/a pwr the center pad on the backsi de of the qfn package is metallic and should be connec ted to gnd on the pcb. the thermal pad size on the pcb should be the approximate size of this center pad and should be sol - der mask defined. the solder mask opening should be at least 0.0025" inwards from the edge of the pcb thermal pad. n.c. - - - 1, 2, 20, 21, 22, 27, 40, 41, 42, 60, 61, 62, 80 no connection. these pins are not used in either the intel or motorola bus modes. pin description n ame 48-qfn p in # 64-lqfp p in # 68-plcc p in # 80-lqfp p in # t ype d escription
xr16v564/564d 9 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 1.0 product description the xr16v564 (v564) integrates the functions of 4 e nhanced 16c550 universal asynchrounous receiver and transmitter (uart). each uart is independently cont rolled and has its own set of device configuration registers. the configuration registers set is 16550 ua rt compatible for control, status and data transfer. additionally, each uart channel has 32 bytes of transmit and receive fifos, automatic rts/cts hardware flow control, automatic xon/xoff and special characte r software flow control, infrared encoder and decoder (irda ver 1.0), programmable fractional baud rate generator with a prescaler of dividing by 1 or 4, and data rate up to 16 mbps. the xr16v564 can operate from 2.25 to 3.6 volts. the v564 is fabricated with an advanced cmos process. enhanced fifo the v564 quart provides a solution that supports 32 by tes of transmit and receive fifo memory, instead of 16 bytes in the st16c554, or one byte in the st16c454. the v564 is designed to work with high performance data communication systems, that require fast data pr ocessing time. increased performance is realized in the v564 by the larger transmit and re ceive fifos, fifo trigger level co ntrol and automatic flow control mechanism. this allows the extern al processor to handle more netw orking tasks within a given time. for example, the st16c554 with a 16 byte fifo, unloads 16 bytes of receive data in 1. 53 ms (this example uses a character length of 11 bits, includ ing start/stop bits at 115.2kbps). this means the external cpu will have to service the receive fifo at 1.53 ms in tervals. however with the 32 byte fi fo in the v564, the data buffer will not require unloading/loading for 3.1 ms. this increases the service interval giving the external cpu additional time for other applications and re ducing the overall uart interrupt servicing time. in addition, the programmable fifo level trigger interrupt and automatic hardware/software flow cont rol is uniquely provided for maximum data throughput performance especially when operating in a multi-channel system. the combination of the above greatly reduces the cpu?s bandwidth requirement, increases performance, and reduces power consumption. data rate the v564 is capable of operation up to 16 mbps at 3. 3v with 4xinternal sampling clock rate. the device can operate at 3.3v with a crystal oscillato r of up to 24 mhz crystal on pins xtal1 and xtal2, or external clock source of 64 mhz on xtal1 pin. with a typical crystal of 14.7456 mhz and through a software option, the user can set the prescaler bit an d sampling rate for data ra tes of up to 3.68 mbps. enhanced features the rich feature set of the v564 is available through the internal register s. automatic hardware/software flow control, selectable transmit and receive fifo trigger le vels, selectable baud rates, infrared encoder/decoder interface, modem interface co ntrols, and a sleep mode ar e all standard feat ures. mcr bit-5 provides a facility for turning off (xon) software flow co ntrol with any incoming (rx) character. in the 16 mode intsel and mcr bit-3 can be configured to provide a software controlled or continuous interrupt capabilit y. for backward compatibility to the st16c654, the 64-p in lqfp does not have the intsel pin. instead, two different lqfp packages are offered. the XR16V564DIV operates in the continuous interrupt enable mode by internally bonding intsel to vcc. the xr16v564iv operates in conjunction with mcr bit-3 by internally bonding intsel to gnd. the xr16v564 offers a clock prescaler select pin to a llow system/board designers to preset the default baud rate table on power up. the clksel pin selects the div-by-1 or div-by-4 prescaler for the baud rate generator. it can then be overridden following initialization by mcr bit-7.
xr16v564/564d 10 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 2.0 functional descriptions 2.1 cpu interface the cpu interface is 8 data bits wide with 3 address li nes and control signals to execute data bus read and write transactions. the v564 data interf ace supports the intel compatible types of cpus and it is compatible to the industry standard 16c550 uart. no clock (oscillator nor external clock) is required for a data bus transaction. each bus cycle is asynchronous using cs# a- d, ior# and iow# or cs#, r/w#, a4 and a3 inputs. all four uart channels share the same data bus for host operations. a typical data bus interconnection for intel and motorola mode is shown in figure 4 . f igure 4. xr16v564 t ypical i ntel /m otorola d ata b us i nterconnections vcc vcc dsra# ctsa# rtsa# dtra# rxa txa ria# cda# gnd a0 a1 a2 uart_csa# uart_csb# ior# iow# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart channel a uart channel b uart_intb uart_inta intb inta uart_reset reset serial interface of rs-232 serial interface of rs-232 intel data bus (16 mode) interconnections uart channel c uart channel d similar to ch a similar to ch a similar to ch a uart_intd uart_intc intd intc uart_csc# uart_csd# csc# csd# vcc 16/68# vcc vcc gnd a0 a1 a2 uart_cs# a3 r/w# d0 d1 d2 d3 d4 d5 d6 d7 a0 a1 a2 csa# csb# d0 d1 d2 d3 d4 d5 d6 d7 ior# iow# uart_irq# intb inta reset# serial interface of rs-232 serial interface of rs-232 motorola data bus (68 mode) interconnections vcc uart_reset# (no connect) dsra# ctsa# rtsa# dtra# rxa txa ria# cda# uart channel a uart channel b uart channel c similar to ch a similar to ch a similar to ch a intc (no connect) intd (no connect) a4 csc# csd# vcc 16/68# uart channel d vcc
xr16v564/564d 11 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 2.2 device reset the reset input resets the internal registers and the seri al interface outputs in both channels to their default state (see ta b l e 17 ). an active high pulse of lo nger than 40 ns du ration will be required to activate the reset function in the device. following a power-on reset or an external reset, the v564 is software compatible with previous generation of uarts, 16c454 and 16c554. 2.3 channel selection the uart provides the user with the capability to bi-directionally tr ansfer information be tween an external cpu and an external serial communication device. during intel bus mode (16/68# pin is connected to vcc), a low on chip select pins, csa#, csb#, csc# or csd# allows the user to select uart channel a, b, c or d to configure, send transmit data and/or unload receive data to/from the uart. selecting all four uarts can be useful during power up initialization to write to the same internal registers, but do not attempt to read from all four uarts simultaneously. individual channel select functions are shown in table 1 . during motorola bus mode (16/68# pin is connected to gnd), the package interface pins are configured for connection with motorola, and other popular microprocessor bus types. in this mode the v564 decodes two additional addresses, a3 and a4, to select one of t he four uart ports. the a3 and a4 address decode function is used only when in the motorola bus mode. see table 2 . t able 1: c hannel a-d s elect in 16 m ode csa# csb# csc# csd# f unction 1 1 1 1 uart de-selected 0 1 1 1 channel a selected 1 0 1 1 channel b selected 1 1 0 1 channel c selected 1 1 1 0 channel d selected 0 0 0 0 channels a-d selected t able 2: c hannel a-d s elect in 68 m ode cs# a4 a3 f unction 1 x x uart de-selected 0 0 0 channel a selected 0 0 1 channel b selected 0 1 0 channel c selected 0 1 1 channel d selected
xr16v564/564d 12 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 2.4 channels a-d internal registers each uart channel in the v564 has a set of enhanced registers for controlling, monitoring and data loading and unloading. the configuration register set is compat ible to those already available in the standard single 16c550. these registers function as data holding registers (thr/rhr), interrupt status and control registers (isr/ier), a fifo control register (fcr), receive line status and contro l registers (lsr/lcr), modem status and control registers (msr/mcr), programmable data ra te (clock) divisor registers (dll/dlm/dld), and a user accessible scratc hpad register (spr). beyond the general 16c550 features an d capabilities, the v564 offers e nhanced feature registers (efr, xon/ xoff 1, xon/xoff 2) that provide automatic rts an d cts hardware flow control and automatic xon/xoff software flow control. all the register fu nctions are discussed in full detail later in ?section 3.0, uart internal registers? on page 24 . 2.5 int ouputs for channels a-d the interrupt outputs change according to the operating mode and enhanced features setup. table 3 and 4 summarize the operating behavior for the transmitter and receiver. also see figure 20 through 25 . 2.6 dma mode the device does not support direct memory access. th e dma mode (a legacy term) in this document does not mean ?direct memory access? but refers to data block transfer operation. the dma mode affects the state of the rxrdy# a-d and txrdy# a-d output pins. the tr ansmit and receive fifo trigger levels provide additional flexibility to the user fo r block mode operation. the lsr bits 5-6 provide an indication when the transmitter is empty or has an empty location(s) for mo re data. the user can optionally operate the transmit and receive fifo in the dma mode (fcr bit-3 = 1). when the transmit and receive fifos are enabled and the dma mode is disabled (fcr bit-3 = 0), the v564 is placed in single-character mode for data transmit or receive operation. when dma mode is enabled (fcr bit-3 = 1), the user takes advantage of block mode operation by t able 3: int p in o peration for t ransmitter for c hannels a-d fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) int pin low = a byte in thr high = thr empty low = fifo above trigger level high = fifo below trigger level or fifo empty low = fifo above trigger level high = fifo below trigger level or fifo empty t able 4: int p in o peration for r eceiver for c hannels a-d fcr b it -0 = 0 (fifo d isabled ) fcr b it -0 = 1 (fifo e nabled ) fcr bit-3 = 0 (dma mode disabled) fcr bit-3 = 1 (dma mode enabled) int pin low = no data high = 1 byte low = fifo below trigger level high = fifo above trigger level low = fifo below trigger level high = fifo above trigger level
xr16v564/564d 13 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo loading or unloading the fifo in a block sequence deter mined by the programmed trigger level. the following table show their behavior. also see figure 20 through 25 . 2.7 crystal oscillator or external clock input the v564 includes an on-chip oscillato r (xtal1 and xtal2) to produce a cl ock for both uart sections in the device. the cpu data bus does not require this clock for bus operation. the crystal oscillator provides a system clock to the baud rate generators (brg) section found in each of the uart. xtal1 is the input to the oscillator or external clock buffer input with xtal2 pin being the output. caution: the xtal1 input is not 5v tolerant. for programming details, see ?section 2.8, programmable baud ra te generator with fractional divisor? on page 13 . the on-chip oscillator is designed to use an industry stand ard microprocessor cryst al (parallel resonant, fundamental frequency with 10-22 pf capacitance load, esr of 20-120 ohms and 100ppm frequency tolerance) connec ted externally be tween the xtal1 and xtal2 pins. typical oscillator connections are shown in figure 5 . alternatively, an external clock can be connected to the xtal1 pin to clock the internal baud rate generator for stan dard or custom rates. for further reading on oscillator ci rcuit please see application note dan108 on exar?s web site. 2.8 programmable baud rate generator with fractional divisor each uart has its own baud rate generator (brg) with a prescaler for the transmitter and receiver. the prescaler is controlled by a software bit in the mcr register. the mcr register bit-7 sets the prescaler to divide the input crystal or external clock by 1 or 4. the outpu t of the prescaler clocks to the brg. the brg further divides this clock by a programmable divisor between 1 an d (216 - 0.0625) in increments of 0.0625 (1/16) to obtain a 16x or 8x or 4x sampling clock of the serial data rate. the sampling clock is used by the transmitter for data bit shifting and receiver for data sampling. the brg divisor (dll, dlm and dld registers) defaults to t able 5: txrdy# and rxrdy# o utputs in fifo and dma m ode for c hannels a-d p ins fcr bit -0=0 (fifo d isabled ) fcr b it -0=1 (fifo e nabled ) fcr b it -3 = 0 (dma m ode d isabled ) fcr b it -3 = 1 (dma m ode e nabled ) rxrdy# low = 1 byte high = no data low = at least 1 byte in fifo high = fifo empty high to low transition when fifo reaches the trigger level, or timeout occurs low to high transition when fifo empties txrdy# low = thr empty high = byte in thr low = fifo empty high = at least 1 byte in fifo low = fifo has at least 1 empty location high = fifo is full f igure 5. t ypical c rystal c onnections c1 22-47pf c2 22-47pf 14.7456 mhz xtal1 xtal2 r=300k to 400k
xr16v564/564d 14 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 the value of ?1? (dll = 0x01, dlm = 0x00 and dld = 0x00) upon reset. therefore, the brg must be programmed during initialization to the operating data rate. the dll and dlm registers provide the integer part of the divisor and the dld register provides the fractional part of the divisor. only the four lower bits of the dld are implemented and they are used to select a value from 0 (for setting 0000) to 0.9375 or 15/16 (for setting 1111). programming the baud rate g enerator registers dll, dlm and dld provides the capability for selecting the operating data rate. table 6 shows the standard data rates available with a 24mhz crystal or external clock at 16x clock rate. if th e pre-scaler is used (mcr bit-7 = 1), the output data rate will be 4 times less than that shown in table 6 . at 8x sampling rate, these data rates would double. and at 4x sampling rate, they would quadruple. also, when using 8x sampling mode, please note that th e bit-time will have a jitter (+/- 1/ 16) whenever the dld is non-zero and is an odd number . when using a non-standard data rate crystal or external clock, the divisor value can be calculated with the following equation(s): the closest divisor that is obtainable in the v5 64 can be calculated using the following formula: in the formulas above, please note that: trunc (n) = integer part of n. for example, trunc (5.6) = 5. round (n) = n rounded towards the cl osest integer. for example, roun d (7.3) = 7 and round (9.9) = 10. a >> b indicates right shifting the value ?a? by ?b? number of bits. for example, 0x78a3 >> 8 = 0x0078. required divisor (decimal)=(xtal1 clock frequency / prescaler) /(serial data rate x 16), with 16x mode, dld[5:4]=?00? required divisor (decimal)= (xtal1 clock frequency / prescaler / (serial data rate x 8), with 8x mode, dld[5:4] = ?01? required divisor (decimal)= (xtal1 clock frequency / prescaler / (serial data rate x 4), with 4x mode, dld[5:4] = ?10? round( (required divisor - trunc(required divisor ) )*16)/16 + trunc( required divisor), where dlm = trunc(required divisor) >> 8 dll = trunc(required divisor) & 0xff dld = round( (required divisor -trunc(required divisor) )*16) f igure 6. b aud r ate g enerator xtal1 xtal2 crystal osc/ buffer mcr bit-7=0 (default) mcr bit-7=1 dll, dlm and dld registers prescaler divide by 1 prescaler divide by 4 16x or 8x or 4x sampling rate clock to transmitter and receiver to other channels fractional baud rate generator logic
xr16v564/564d 15 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 2.9 transmitter the transmitter section comprises of an 8-bit transmit shift register (tsr) and 32 bytes of fifo which includes a byte-wide transmit holding register (thr) . tsr shifts out every data bit with the 16x/8x/4x internal clock. a bit time is 16/8/4 clock periods. th e transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled, and a dds the stop-bit(s). the stat us of the fifo and tsr are reported in the line status register (lsr bit-5 and bit-6). 2.9.1 transmit holding regi ster (thr) - write only the transmit holding register is an 8-bit register pr oviding a data interface to the host processor. the host writes transmit data byte to the thr to be converted in to a serial data stream including start-bit, data bits, parity-bit and stop-bit(s). the least-si gnificant-bit (bit-0) becomes first data bit to go out. the thr is the input register to the transmit fifo of 32 bytes when fifo operation is enabl ed by fcr bit-0. every time a write operation is made to the thr, the fifo data pointer is automatically bumped to the next sequential data location. t able 6: t ypical data rates with a 24 mh z crystal or external clock at 16x s ampling required output data rate d ivisor for 16x clock (decimal) d ivisor o btainable in v2550 dlm p rogram v alue (hex) dll p rogram v alue (hex) dld p rogram v alue (hex) d ata e rror r ate (%) 400 3750 3750 e a6 0 0 2400 625 625 2 71 0 0 4800 312.5 312 8/16 1 38 8 0 9600 156.25 156 4/16 0 9c 4 0 10000 150 150 0 96 0 0 19200 78.125 78 2/16 0 4e 2 0 25000 60 60 0 3c 0 0 28800 52.0833 52 1/16 0 34 1 0.04 38400 39.0625 39 1/16 0 27 1 0 50000 30 30 0 1e 0 0 57600 26.0417 26 1/16 0 1a 1 0.08 75000 20 20 0 14 0 0 100000 15 15 0 f 0 0 115200 13.0208 13 0 d 0 0.16 153600 9.7656 9 12/16 0 9 c 0.16 200000 7.5 7 8/16 0 7 8 0 225000 6.6667 6 11/16 0 6 b 0.31 230400 6.5104 6 8/16 0 6 8 0.16 250000 6 6 0 6 0 0 300000 5 5 0 5 0 0 400000 3.75 3 12/16 0 3 c 0 460800 3.2552 3 4/16 0 3 4 0.16 500000 3 3 0 3 0 0 750000 2 2 0 2 0 0 921600 1.6276 1 10/16 0 1 a 0.16 1000000 1.5 1 8/16 0 1 8 0
xr16v564/564d 16 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 2.9.2 transmitter operation in non-fifo mode the host loads transmit data to thr one character at a time. the thr empty flag (lsr bit-5) is set when the data byte is transferred to tsr. thr flag can generate a tr ansmit empty interrupt (isr bit-1) when it is enabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr beco mes completely empty. 2.9.3 transmitter operation in fifo mode the host may fill the transmit fifo with up to 32 bytes of transmit data. t he thr empty flag (lsr bit-5) is set whenever the fifo is empty. the thr empty flag can ge nerate a transmit empty interrupt (isr bit-1) when the fifo becomes empty. the transmit empty interrupt is e nabled by ier bit-1. the tsr flag (lsr bit-6) is set when tsr/fifo becomes empty. f igure 7. t ransmitter o peration in non -fifo m ode f igure 8. t ransmitter o peration in fifo and f low c ontrol m ode transmit holding register (thr) transmit shift register (tsr) data byte l s b m s b thr interrupt (isr bit-1) enabled by ier bit-1 txnofifo1 16x or 8x or 4x clock ( dld[5:4] ) transmit data shift register (tsr) transmit data byte thr interrupt (isr bit-1) falls below the programmed trigger level and then when becomes empty. fifo is enabled by fcr bit-0=1 transmit fifo 16x or 8x or 4x clock (dld[5:4]) auto cts flow control (cts# pin) auto software flow control flow control characters (xoff1/2 and xon1/2 reg.) txfifo1
xr16v564/564d 17 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 2.10 receiver the receiver section contains an 8-bit receive shift register (rsr) and 32 bytes of fifo which includes a byte-wide receive holding register (rhr). the rsr uses the 16x/8x/4x clock (dld[5:4]) for timing. it verifies and validates every bit on the incoming character in the middle of each data bit. on the falling edge of a start or false start bit, an internal receiver counter starts counting at the 16x/8x/4x clock rate. after 8 clocks (or 4 if 8x or 2 if 4x) the start bit pe riod should be at the center of the start bit. at this time the start bit is sampled and if it is still low it is validated. evaluating the start bit in this manner prevents the receiver from assembling a false character. the rest of the data bits and stop bits are sampled and validated in this same manner to prevent false framing. if th ere were any error(s), they are reported in the lsr register bits 2-4. upon unloading the receive data byte from rhr, the rece ive fifo pointer is bumped and the error tags are immediately updated to reflect the status of the data byte in rhr register. rhr can generate a receive data ready interrupt upon receiving a character or delay unti l it reaches the fifo trigger level. furthermore, data delivery to the host is guaranteed by a receive data read y time-out interrupt when data is not received for 4 word lengths as defined by lcr[1:0] plus 12 bits time. this is equivalent to 3.7-4. 6 character times. the rhr interrupt is enabled by ier bit-0. see figure 9 and figure 10 below. 2.10.1 receive holding register (rhr) - read-only the receive holding register is an 8-bit register that holds a receive data byte from the receive shift register. it provides the receive data interface to the host processor. the rhr register is part of the receive fifo of 32 bytes by 11-bits wide, the 3 extra bits are fo r the 3 error tags to be reported in lsr register. when the fifo is enabled by fcr bit-0, the rhr contains th e first data character received by the fifo. after the rhr is read, the next character byte is loaded into the rhr and the errors associated with the current data byte are immediately updated in the lsr bits 2-4. f igure 9. r eceiver o peration in non -fifo m ode receive data shift register (rsr) receive data byte and errors rhr interrupt (isr bit-2) receive data holding register (rhr) rxfifo1 16x or 8x or 4x clock ( dld[5:4] ) receive data characters data bit validation error tags in lsr bits 4:2
xr16v564/564d 18 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 2.11 auto rts (hardware) flow control automatic rts hardware flow control is used to prevent data overrun to the local receiver fifo. the rts# output is used to request remote unit to suspend/r esume data transmission. the auto rts flow control features is enabled to fit specific application requirement (see figure 11 ): ? enable auto rts flow control using efr bit-6. ? the auto rts function must be started by asserting rts# output pin (mcr bit-1 to logic 1 after it is enabled). if using the auto rts interrupt: enable rts interrupt through ier bit-6 (after setting efr bit-4). the ua rt issues an interr upt when the rts# pin makes a transition from low to high: isr bit-5 will be set to logic 1. 2.12 auto rts hysteresis the v564 has a new feature that provides flow control trigger hyst eresis while maintaining compatibility with the xr16c850, st16c650a and st16c550 family of uarts. with the auto rts functi on enabled, an interrupt is generated when the receive fifo reaches the sele cted rx trigger level. the rts# pin will not be forced high (rts off) until the receive fifo reaches one trigger level above the selected trigger level in the trigger table ( table 12 ). the rts# pin will return low after the rx fifo is unloaded to one level be low the selected trigger level. under the abov e described conditions, the v564 will continue to acce pt data until the receive fifo gets full. the auto rts function is initiated when the rts# output pin is asserted low (rts on). f igure 10. r eceiver o peration in fifo and a uto rts f low c ontrol m ode t able 7: a uto rts (h ardware ) f low c ontrol r x t rigger l evel int p in a ctivation rts# d e - asserted (h igh ) (c haracters in r x f ifo ) rts# a sserted (l ow ) (c haracters in r x f ifo ) 8 8 16 0 16 16 24 8 24 24 30 16 30 30 30 24 receive data shift register (rsr) rxfifo1 16x or 8x or 4x clock ( dld[5:4] ) error tags (32-sets) error tags in lsr bits 4:2 receive data characters data bit validation receive data fifo receive data receive data byte and errors rhr interrupt (isr bit-2) programmed for desired fifo trigger level. fifo is enabled by fcr bit-0=1 rts# de-asserts when data fills above the flow control trigger level to suspend remote transmitter. enable by efr bit-6=1, mcr bit-1. rts# re-asserts when data falls below the flow control trigger level to restart remote transmitter. enable by efr bit-6=1, mcr bit-1. 32 bytes by 11-bit wide fifo fifo trigger=16 data falls to 8 data fills to 24 example : - rx fifo trigger level selected at 16 bytes (see note below)
xr16v564/564d 19 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 2.13 auto cts flow control automatic cts flow control is used to prevent data overrun to the remote receiver fifo. the cts# input is monitored to suspend/restart the local transmitter. the aut o cts flow control feature is selected to fit specific application requirement (see figure 11 ): ? enable auto cts flow control using efr bit-7. if needed, the cts interrupt can be enabled through ier bi t-7 (after setting efr bit-4). the uart issues an interrupt when the cts# pin is de-asserted (high) : isr bit-5 will be set to 1, and uart will suspend transmission as soon as the stop bit of the character in process is shifted out. transmission is resumed after the cts# input is re-asserted (low), indicating more data may be sent. f igure 11. a uto rts and cts f low c ontrol o peration the local uart (uarta) starts data transfer by asserting rtsa# (1). rtsa# is normally connected to ctsb# (2) of remote uart (uartb). ctsb# allows its transmitter to se nd data (3). txb data arrives and fills uarta receive fifo (4). when rxa data fills up to its receive fifo trigger le vel, uarta activates its rxa data ready interrupt (5) and con - tinues to receive and put data into its fifo. if interrupt se rvice latency is long and data is not being unloaded, uarta monitors its receive data fill level to match the upper thre shold of rts delay and de-assert rtsa# (6). ctsb# follows (7) and request uartb transmitter to suspend data transfer. ua rtb stops or finishes sending the data bits in its trans - mit shift register (8). when receive fifo data in uarta is unloaded to match the lower threshold of rts delay (9), uarta re-asserts rtsa# (10), ctsb# recognizes the change (11) and restarts its transmitter and data flow again until next receive fifo trigger (12). this same event applies to the reverse direction when uarta sends data to uartb with rtsb# and ctsa# controlling the data flow. rtsa# ctsb# rxa txb transmitter receiver fifo trigger reached auto rts trigger level auto cts monitor rtsa# txb rxa fifo ctsb# remote uart uartb local uart uarta on off on suspend restart rts high threshold data starts on off on assert rts# to begin transmission 1 2 3 4 5 6 7 receive data rts low threshold 9 10 11 receiver fifo trigger reached auto rts trigger level transmitter auto cts monitor rtsb# ctsa# rxb txa inta (rxa fifo interrupt) rx fifo trigger level rx fifo trigger level 8 12 rtscts1
xr16v564/564d 20 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 2.14 auto xon/xoff (software) flow control when software flow control is enabled ( see table 16 ), the v564 compares one or two sequential receive data characters with the programmed xon or xoff-1,2 charac ter value(s). if receive character(s) (rx) match the programmed values, the v564 will halt transmission (tx) as soon as th e current character has completed transmission. when a match occurs, the xoff (if enabled vi a ier bit-5) flag will be set and the interrupt output pin will be activated. following a suspension due to a matc h of the xoff character, the v564 will monitor the receive data stream for a match to th e xon-1,2 character. if a match is fo und, the v564 will resume operation and clear the flags (isr bit-4). reset initially sets the contents of the xon/xoff 8-bit flow control registers to low. following reset the user can write any xon/xoff value desired for software flow cont rol. different conditions can be set to detect xon/xoff characters ( see table 16 ) and suspend/resume transmissions. when double 8-bit xon/xoff characters are selected, the v564 compares two consecutive receive c haracters with two software flow control 8-bit values (xon1, xon2, xoff1, xoff2) and controls tx transmissi ons accordingly. under the above described flow control mechanisms, flow control characters are not placed (sta cked) in the user accessible rx data buffer or fifo. in the event that the receive buffer is overfilling and flow control needs to be executed, the v 564 automatically sends an xoff message (when enabled) via the serial tx output to the remote modem. the v564 sends the xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate) after the receive fifo crosses the pr ogrammed trigger level. to clear this condition, the v564 will transmit the programmed xon-1,2 characters as soon as receive fifo is less than one trigge r level below the programmed trigger level. table 8 below explains this. * after the trigger level is reached, an xoff character is s ent after a short span of time (= time required to send 2 characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting. 2.15 special character detect a special character detect feature is provided to detect an 8-bit character when bit-5 is set in the enhanced feature register (efr). when this character (xoff2) is detected, it will be placed in the fi fo along with normal incoming rx data. the v564 compares each incoming receiv e character with xoff-2 data. if a match exists, the received data will be transferred to the rx fi fo and isr bit-4 will be set to indicate de tection of special ch aracter. although the internal register table shows xon, xoff registers with ei ght bits of character information, the actual number of bits is dependent on the programmed word length. line cont rol register (lcr) bits 0-1 defines the number of character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. the word length selected by lcr bits 0-1 also determines the number of bits that will be used for the special character comparison. bit-0 in the xon, xoff registers corresponds with the ls b bit for the receive character. t able 8: a uto x on /x off (s oftware ) f low c ontrol rx t rigger l evel int p in a ctivation x off c haracter ( s ) s ent ( characters in rx fifo ) x on c haracter ( s ) s ent ( characters in rx fifo ) 8 8 8* 0 16 16 16* 8 24 24 24* 16 30 30 30* 24
xr16v564/564d 21 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 2.16 infrared mode the v564 uart includes the infrared encoder and decoder compatible to the irda (infrared data association) version 1.0. the irda 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit wide high- pulse for each ?0? bit in the transmit data stream. this signal encoding reduces the on-time of the infrared led, hence reduces the power consumption. see figure 12 below. the infrared encoder and decoder are enabled by setting mcr register bit-6 to a ?1?. when the infrared feature is enabled, the transmit data output, tx, idles at logic zero level. likewise, the rx input assumes an idle level of logic zero from a reset and power up, see figure 12 . typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the rx pin. each time it senses a light pulse, it returns high to the data bit stream. f igure 12. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding character data bits start stop 0000 0 11 111 bit time 1/16 clock delay irdecoder-1 rx data receive ir pulse (rx pin) character data bits start stop 0000 0 11 111 tx data transmit ir pulse (tx pin) bit time 1/2 bit time 3/16 bit time irencoder-1
xr16v564/564d 22 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 2.17 sleep mode with auto wake-up the v564 supports low voltage system designs, hence, a sleep mode is included to reduce its power consumption when the chip is not actively used. all of these conditions must be sati sfied for the v564 to enter sleep mode: no interrupts pending for all four channels of the v564 (isr bit-0 = 1) sleep mode of all channels are enabled (ier bit-4 = 1) modem inputs are not toggling (msr bits 0-3 = 0) rx input pins are idling high the v564 stops its crystal oscillator to conserve power in the sleep mode. user can check the xtal2 pin for no clock output as an indication that the device has entered the sleep mode. the v564 resumes normal operation by any of the following: a receive data start bit transition (high to low) a data byte is loaded to the transmitter, thr or fifo a change of logic state on any of the modem or general purpose serial inputs: cts#, dsr#, cd#, ri# if the v564 is awakened by any one of the above conditions, it will return to the sleep mo de automatically after all interrupting conditions have been serviced and clea red. if the v564 is awak ened by the modem inputs, a read to the msr is required to re set the modem inputs. in any case, t he sleep mode will not be entered while an interrupt is pendi ng from any channel. the v564 will stay in the sl eep mode of operation until it is disabled by setting ier bit-4 to a logic 0. if the address lines, data bus lines, iow#, ior#, csa# , csb#, csc#, csd# and mo dem input lines remain steady when the v564 is in sleep mode, the maximum current will be in the microamp range as specified in the dc electrical characteristics on page 40 . if the input lines are floating or are toggling while the v564 is in sleep mode, the current can be up to 100 times more. if any of those signals are toggling or floating, then an external buffer would be required to keep the address, da ta and control lines steady to achieve the low current. a word of caution: owing to the star ting up delay of the crystal oscillato r after waking up from sleep mode, the first few receive characters may be lost. also, make sure the rx a-d pins are idling high or ?marking? condition during sleep mode. this may not occur when th e external interface transc eivers (rs-232, rs-485 or another type) are also put to sleep mode and cannot maintain the ?marking? condition. to avoid this, the system design engineer can use a 47k ohm pull-up resistor on each of the rx a-d inputs. 2.18 internal loopback the v564 uart provides an internal loopback capability for system diagnostic purposes . the internal loopback mode is enabled by setting mcr register bit-4 to logi c 1. all regular uart functions operate normally. figure 13 shows how the modem port signals are re-configured. transmit data from the transmit shift register output is internally routed to the receive shift register input allowing the system to re ceive the same data that it was sending. the tx pin is held high or mark condition while rts# and dtr# are de-asserted, and cts#, dsr# cd# and ri# inputs are ignored. caution: the rx input must be held high during loopback test else upon exiting the loopback test the uart may detect and report a false ?break? signal.
xr16v564/564d 23 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo f igure 13. i nternal l oop b ack in c hannel a and b tx a-d rx a-d modem / general purpose control logic internal data bus lines and control signals rts# a-d mcr bit-4=1 vcc vcc transmit shift register (thr/fifo) receive shift register (rhr/fifo) cts# a-d dtr# a-d dsr# a-d ri# a-d cd# a-d op1# op2# rts# cts# dtr# dsr# ri# cd# vcc
xr16v564/564d 24 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 3.0 uart internal registers each uart channel in the v564 has its own set of configuration registers selected by address lines a0, a1 and a2 with a specific channel selected (see table 1 and table 2 ). the complete register set is shown on table 9 and table 10 . t able 9: uart channel a and b uart internal registers a2,a1,a0 a ddresses r egister r ead /w rite c omments 16c550 c ompatible r egisters 0 0 0 rhr - receive holding register thr - transmit holding register read-only write-only lcr[7] = 0 0 0 0 dll - divisor lsb read/write lcr[7] = 1, lcr 0xbf 0 0 1 dlm - divisor msb read/write 0 1 0 dld - divisor fractional read/write 0 0 1 ier - interrupt enable register read/write lcr[7] = 0 0 1 0 isr - interrupt status register fcr - fifo control register read-only write-only 0 1 1 lcr - line control register read/write 1 0 0 mcr - modem control register read/write lcr[7] = 0 1 0 1 lsr - line status register read/write 1 1 0 msr - modem status register read/write 1 1 1 spr - scratch pad register read/write e nhanced r egisters 0 1 0 efr - enhanced function reg read/write lcr = 0xbf 1 0 0 xon-1 - xon character 1 read/write 1 0 1 xon-2 - xon character 2 read/write 1 1 0 xoff-1 - xoff character 1 read/write 1 1 1 xoff-2 - xoff character 2 read/write
xr16v564/564d 25 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo t able 10: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment 16c550 compatible registers 0 0 0 rhr rd bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7] = 0 0 0 0 thr wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 0 1 ier rd/wr 0/ 0/ 0/ 0/ modem stat. int. enable rx line stat. int. enable tx empty int enable rx data int. enable cts# int. enable rts# int. enable xoff int. enable sleep mode enable 0 1 0 isr rd fifos enabled fifos enabled 0/ 0/ int source bit-3 int source bit-2 int source bit-1 int source bit-0 rts cts int xoff int 0 1 0 fcr wr rx fifo trigger rx fifo trigger 0/ 0/ dma mode enable tx fifo reset rx fifo reset fifos enable tx fifo trigger tx fifo trigger 0 1 1 lcr rd/wr divisor enable set tx break set parity even parity parity enable stop bits word length bit-1 word length bit-0 1 0 0 mcr rd/wr 0/ 0/ 0/ internal lopback enable int out - put enable (op2#) rsvd (op1#) rts# output control dtr# output control lcr[7] = 0 brg pres - caler ir mode enable xon any 1 0 1 lsr rd/wr rx fifo global error thr & tsr empty thr empty rx break rx framing error rx parity error rx over - run error rx data ready 1 1 0 msr rd/wr cd# input ri# input dsr# input cts# input delta cd# delta ri# delta dsr# delta cts# 1 1 1 spr rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 baud rate generator divisor 0 0 0 dll rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 lcr[7]=1 lcr 0xbf 0 0 1 dlm rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 0 1 0 dld rd/wr rsvd rsvd 4x mode 8x mode bit-3 bit-2 bit-1 bit-0 lcr[7] = 1 lcr 0xbf efr[4] = 1
xr16v564/564d 26 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 4.0 internal register descriptions 4.1 receive holding register (rhr) - read- only see?receiver? on page 17. 4.2 transmit holding register (thr) - write-only see?transmitter? on page 15. 4.3 interrupt enable register (ier) - read/write the interrupt enable register (ier) masks the interrupts from receive data ready, transmit empty, line status and modem status registers. these interrupts are r eported in the interrupt status register (isr). 4.3.1 ier versus receive fifo interrupt mode operation when the receive fifo (fcr bit-0 = 1) and receive inte rrupts (ier bit-0 = 1) are enabled, the rhr interrupts (see isr bits 2 and 3) status will reflect the following: a. the receive data available interrupts are issued to the host when the fifo has reached the programmed trigger level. it will be cleared when the fifo drops below the programmed trigger level. b. fifo level will be reflected in the isr register when the fifo trigger level is reached. both the isr register status bit and the interrupt will be cleared wh en the fifo drops below the trigger level. c. the receive data ready bit (lsr bit-0) is set as soon as a character is transferred from the shift register to the receive fifo. it is rese t when the fifo is empty. enhanced registers 0 1 0 efr rd/wr auto cts# enable auto rts# enable special char select enable ier [7:4], isr [5:4], fcr[5:4], mcr[7:5], dld soft- ware flow cntl bit-3 soft - ware flow cntl bit-2 soft - ware flow cntl bit-1 soft - ware flow cntl bit-0 lcr=0 x bf 1 0 0 xon1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 0 1 xon2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 0 xoff1 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 1 1 1 xoff2 rd/wr bit-7 bit-6 bit-5 bit-4 bit-3 bit-2 bit-1 bit-0 t able 10: internal registers description. s haded bits are enabled when efr b it -4=1 a ddress a2-a0 r eg n ame r ead / w rite b it -7 b it -6 b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 c omment
xr16v564/564d 27 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 4.3.2 ier versus receive/transmit fifo polled mode operation when fcr bit-0 equals a logic 1 for fifo enable; rese tting ier bits 0-3 enables the xr16v564 in the fifo polled mode of operation. since the receiver and transmitter have separate bits in the lsr either or both can be used in the polled mode by selecting respective transmit or receive control bit(s). a. lsr bit-0 indicates there is data in rhr or rx fifo. b. lsr bit-1 indicates an overrun error has occurred and that data in the fifo may not be valid. c. lsr bit 2-4 provides the type of receive data erro rs encountered for the data byte in rhr, if any. d. lsr bit-5 indicates thr is empty. e. lsr bit-6 indicates when both the transmit fifo and tsr are empty. f. lsr bit-7 indicates a data error in at least one character in the rx fifo. ier[0]: rhr interrupt enable the receive data ready interrupt will be issued when rhr has a data characte r in the non-fifo mode or when the receive fifo has reached the programmed trigger level in the fifo mode. logic 0 = disable the receive data ready interrupt (default). logic 1 = enable the receiver data ready interrupt. ier[1]: thr interrupt enable this bit enables the transmit ready interrupt which is issued whenever the thr becomes empty in the non- fifo mode or when data in the fifo fa lls below the programmed trigger level in the fifo mode. if the thr is empty when this bit is enabled , an interrupt will be generated. logic 0 = disable transmit ready interrupt (default). logic 1 = enable transmit ready interrupt. ier[2]: receive line status interrupt enable if any of the lsr register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller about the error status of the current data byte in fifo . lsr bit-1 generates an interrupt immediately when an overrun occurs. lsr bits 2-4 generate an interrupt when the character in the rhr has an error. ? logic 0 = disable the receiver line status interrupt (default). ? logic 1 = enable the receiver line status interrupt. ier[3]: modem status interrupt enable ? logic 0 = disable the modem status register interrupt (default). ? logic 1 = enable the modem status register interrupt. ier[4]: sleep mode enable (requires efr[4] = 1) ? logic 0 = disable sleep mode (default). ? logic 1 = enable sleep mode. see sleep mode section for further details. ier[5]: xoff interrupt enable (requires efr[4]=1) ? logic 0 = disable the software flow cont rol, receive xoff interrupt. (default) ? logic 1 = enable the software flow control, receive xoff interrupt. see software flow control section for details.
xr16v564/564d 28 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 ier[6]: rts# output interrupt enable (requires efr[4]=1) ? logic 0 = disable the rts# interrupt (default). ? logic 1 = enable the rts# interrupt. the uart issues an interrupt when the rts# pin makes a transition from low to high (if enabled by efr bit-6). ier[7]: cts# input interrupt enable (requires efr[4]=1) ? logic 0 = disable the cts# interrupt (default). ? logic 1 = enable the cts# interrupt. the uart issues an interrupt when cts# pin makes a transition from low to high (if enabled by efr bit-7). 4.4 interrupt status register (isr) - read-only the uart provides multiple levels of prioritized interrupts to minimize external software interaction. the interrupt status register (isr) provides the user with six interrupt status bits. performing a read cycle on the isr will give the user the current hi ghest pending interrupt le vel to be serviced, others are queued up to be serviced next. no other interrupts are acknowledged until the pending interrupt is serviced. the interrupt source table, table 11 , shows the data values (bit 0-5) for the inte rrupt priority levels and the interrupt sources associated with each of these interrupt levels. 4.4.1 interrupt generation: ? lsr is by any of the lsr bits 1, 2, 3 and 4. ? rxrdy is by rx trigger level. ? rxrdy time-out is by a 4-char plus 12 bits delay timer. ? txrdy is by tx trigger level or tx fifo empty. ? msr is by any of the msr bits 0, 1, 2 and 3. ? receive xoff/special character is by det ection of a xoff or special character. ? cts# is when the remote tr ansmitter toggles the input pin (from low to high) during auto cts flow control. ? rts# is when its receiver toggles the output pin (f rom low to high) during auto rts flow control. 4.4.2 interrupt clearing: ? lsr interrupt is cleared by a read to the lsr register. ? rxrdy interrupt is cleared by reading data until fifo falls be low the trigger level. ? rxrdy time-out interrupt is cleared by reading rhr. ? txrdy interrupt is cleared by a read to the isr register or writing to thr. ? msr interrupt is cleared by a read to the msr register. ? xoff interrupt is cleared by a read to the isr register or wh en xon character(s) is received. ? special character interrupt is cleared by a read to isr register or after next character is received. ? rts# and cts# flow control interrupts are cleared by a read to the msr register.
xr16v564/564d 29 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo ] isr[0]: interrupt status ? logic 0 = an interrupt is pending and the isr contents ma y be used as a pointer to the appropriate interrupt service routine. ? logic 1 = no interrupt pending (default condition). isr[3:1]: interrupt status these bits indicate the source for a pending interrupt at interrupt priority leve ls (see interrupt source table 11 ). isr[4]: interrupt status (requires efr bit-4 = 1) this bit is enabled when efr bit-4 is set to a logic 1. is r bit-4 indicates that the receiver detected a data match of the xoff character(s) or a special character. isr[5]: interrupt status (requires efr bit-4 = 1) isr bit-5 indicates that cts# or rts# has changed state from low to high. isr[7:6]: fifo enable status these bits are set to a logic 0 when the fifos are disa bled. they are set to a logic 1 when the fifos are enabled. 4.5 fifo control register (fcr) - write-only this register is used to enable the fifos, clear the fifos, set the transm it/receive fifo trigger levels, and select the dma mode. the dma, and fifo modes are defined as follows: fcr[0]: tx and rx fifo enable ? logic 0 = disable the transmit and receive fifo (default). ? logic 1 = enable the transmit and receive fifos. this bit must be set to logic 1 when other fcr bits are written or they will not be programmed. t able 11: i nterrupt s ource and p riority l evel p riority isr r egister s tatus b its s ource of interrupt l evel b it -5 b it -4 b it -3 b it -2 b it -1 b it -0 1 0 0 0 1 1 0 lsr (receiver line status register) 2 0 0 1 1 0 0 rxrdy (receive data time-out) 3 0 0 0 1 0 0 rxrdy (received data ready) 4 0 0 0 0 1 0 txrdy (transmit ready) 5 0 0 0 0 0 0 msr (modem status register) 6 0 1 0 0 0 0 rxrdy (received xoff or special character) 7 1 0 0 0 0 0 cts#, rts# change of state - 0 0 0 0 0 1 none (default)
xr16v564/564d 30 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 fcr[1]: rx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no receive fifo reset (default) ? logic 1 = reset the receive fifo pointers and fifo le vel counter logic (the rece ive shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[2]: tx fifo reset this bit is only active when fcr bit-0 is a ?1?. ? logic 0 = no transmit fifo reset (default). ? logic 1 = reset the transmit fifo pointers and fifo le vel counter logic (the transmit shift register is not cleared or altered). this bit will return to a logic 0 after resetting the fifo. fcr[3]: dma mode select controls the behavior of the -txrdy and -rxrdy pins. see dma operation section for details. ? logic 0 = normal operation (default). ? logic 1 = dma mode. fcr[5:4]: transmit fifo trigger select (requires efr bit-4 = 1) (logic 0 = default, tx trigger level = one) these 2 bits set the trigger level for the transmit fifo. the uart will issue a transmit interrupt when the number of characters in the fifo falls below the selected trigger level, or when it gets empty in case that the fifo did not get filled over the trigger level on last re-load. table 12 below shows the selections. fcr[7:6]: receive fifo trigger select (logic 0 = default, rx trigger level =1) these 2 bits are used to se t the trigger level for the receive fifo. th e uart will issue a rece ive interrupt when the number of the characters in the fifo crosses the trigger level. table 12 shows the comple te selections. t able 12: t ransmit and r eceive fifo t rigger l evel s election fcr b it -7 fcr b it -6 fcr b it -5 fcr bit -4 r eceive t rigger l evel t ransmit t rigger l evel 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 8 16 24 30 16 8 24 30
xr16v564/564d 31 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 4.6 line control register (lcr) - read/write the line control register is used to specify the asynchronous data communication format. the word or character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this register. lcr[1:0]: tx and rx word length select these two bits specify the word length to be transmitted or received. lcr[2]: tx and rx stop-bit length select the length of stop bit is specified by this bi t in conjunction with the programmed word length. lcr[3]: tx and rx parity select parity or no parity can be selected via this bit. the pa rity bit is a simple way used in communications for data integrity check. see table 13 for parity selection summary below. ? logic 0 = no parity. ? logic 1 = a parity bit is generated duri ng the transmission while the receiver checks for parity error of the data character received. lcr[4]: tx and rx parity select if the parity bit is enabled with lcr bit-3 set to a logi c 1, lcr bit-4 selects the even or odd parity format. ? logic 0 = odd parity is generated by forcing an odd number of logic 1?s in the transmitted character. the receiver must be programmed to check the same format (default). ? logic 1 = even parity is gen erated by forcing an even numb er of logic 1?s in the tr ansmitted character. the receiver must be programmed to check the same format. bit-1 bit-0 w ord length 0 0 5 (default) 0 1 6 1 0 7 1 1 8 bit-2 w ord length s top bit length (b it time ( s )) 0 5,6,7,8 1 (default) 1 5 1-1/2 1 6,7,8 2
xr16v564/564d 32 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 lcr[5]: tx and rx parity select if the parity bit is enabled, lcr bit- 5 selects the forced parity format. ? lcr bit-5 = low, parity is not forced (default). ? lcr bit-5 = high and lcr bit-4 = low, parity bit is fo rced to a logical 1 for the transmit and receive data. ? lcr bit-5 = high and lcr bit-4 = low, parity bit is fo rced to a logical 0 for the transmit and receive data. lcr[6]: transmit break enable when enabled, the break control bit causes a break cond ition to be transmitted (the tx output is forced to a ?space?, low, state). this condit ion remains, until disabled by setting lcr bit-6 to a logic 0. ? logic 0 = no tx break condition. (default) ? logic 1 = forces the transmitter output (tx) to a ?spa ce?, low, for alerting the remote receiver of a line break condition. lcr[7]: baud rate divisors enable baud rate generator divisor (dll/dlm/dld) enable. ? logic 0 = data registers are selected. (default) ? logic 1 = divisor latch registers are selected. 4.7 modem control register (mcr) or general purpose outputs control - read/write the mcr register is used for contro lling the serial/modem interface signal s or general pur pose inputs/outputs. mcr[0]: dtr# output the dtr# pin is a modem control outpu t. if the modem interface is not us ed, this output may be used as a general purpose output. ? logic 0 = force dtr# output high (default). ? logic 1 = force dtr# output low. mcr[1]: rts# output the rts# pin is a modem control output and may be used for automatic hardware flow control by enabled by efr bit-6. if the modem interface is not used, this output may be used as a general purpose output. ? logic 0 = force rts# output high (default). ? logic 1 = force rts# output low. mcr[2]: reserved op1# is not available as an output pin on the v564. but it is available for use during internal loopback mode. in the loopback mode, this bit is used to writ e the state of the modem ri# interface signal. t able 13: p arity selection lcr b it -5 lcr b it -4 lcr b it -3 p arity selection x x 0 no parity 0 0 1 odd parity 0 1 1 even parity 1 0 1 force parity to mark, high 1 1 1 forced parity to space, low
xr16v564/564d 33 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo mcr[3]: int output enable enable or disable int outputs to become active or in three-state. this function is associated with the intsel input, see below table for details. this bit is also used to control the op2# signal during internal loopback mode. intsel pin must be low during 68 mode. ? logic 0 = int (a-d) outputs disabled (three state) in the 16 mode (default). during internal loopback mode, op2# is high. ? logic 1 = int (a-d) outputs enabled (active) in the 16 mode. during internal loopback mode, op2# is low. mcr[4]: internal loopback enable ? logic 0 = disable loopback mode (default). ? logic 1 = enable local loopback mode, see loopback section and figure 13 . mcr[5]: xon-any enable (requires efr bit-4 = 1) ? logic 0 = disable xon-any function (for 16c550 compat ibility, default). ? logic 1 = enable xon-any function. in this mode, any rx character rece ived will resume transmit operation. the rx character will be loaded into the rx fifo , unless the rx character is an xon or xoff character and the v564 is programmed to use the xon/xoff flow control. mcr[6]: infrared encoder/decoder enable (requires efr bit-4 = 1) ? logic 0 = enable the standard modem receive an d transmit input/output interface. (default) ? logic 1 = enable infrared irda receive and transmit inputs/outputs. the tx/rx output/input are routed to the infrared encoder/decoder. the data input and output levels conform to the irda infrared interface requirement. the rx fifo may need to be flushed upon enable. while in this mode, the infrared tx output will be low during idle data conditions. mcr[7]: clock prescaler select (requires efr bit-4 = 1) ? logic 0 = divide by one. the input clock from the crystal or external clock is fed directly to the programmable baud rate generator without further modification, i.e., divide by one (default). ? logic 1 = divide by four. the prescaler divides the input clock from the crystal or external clock by four and feeds it to the programmable baud rate generator, hence, data rates become one forth. t able 14: int o utput m odes intsel p in mcr b it -3 int a-d o utputs in 16 m ode 0 0 three-state 0 1 active 1 x active
xr16v564/564d 34 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 4.8 line status register (lsr) - read/write this register is writeable but it is not recommended. th e lsr provides the status of data transfers between the uart and the host. if ier bit-2 is enabled, lsr bit 1 will generate an interrupt immediately and lsr bits 2-4 will generate an inte rrupt when a char acter with an error is in the rhr. lsr[0]: receive data ready indicator ? logic 0 = no data in receive holding register or fifo (default). ? logic 1 = data has been received and is save d in the receive holding register or fifo. lsr[1]: receiver overrun flag ? logic 0 = no overrun error (default). ? logic 1 = overrun error. a data overrun error condition occurred in the receive shift register. this happens when additional data arrives while the fi fo is full. in this case the previous data in the receive shift register is overwritten. note that under this condition the data byte in the receive shift register is not transferred into the fifo, therefore the data in the fifo is not corrupted by the error. lsr[2]: receive data parity error tag ? logic 0 = no parity error (default). ? logic 1 = parity error. the receive character in rhr does not have correct pa rity information and is suspect. this error is associated with the char acter available for reading in rhr. lsr[3]: receive data framing error tag ? logic 0 = no framing error (default). ? logic 1 = framing error. the receive character did not hav e a valid stop bit(s). this error is associated with the character available for reading in rhr. lsr[4]: receive break tag ? logic 0 = no break condition (default). ? logic 1 = the receiver received a break signal (rx wa s low for at least one character frame time). in the fifo mode, only one break character is loaded into the fifo. the break indication remains until the rx input returns to the idle condition, ?mark? or high. lsr[5]: transmit holding register empty flag this bit is the transmit holding register empty indicator. the thr bit is set to high when the last data byte is transferred from the transmit holding register to the transmit shift register. the bit is reset to logic 0 concurrently with the data loading to the transmit holding register by the host. in the fifo mode this bit is set when the transmit fifo is empty, it is cleared when the transmit fifo contains at least 1 byte. lsr[6]: thr and tsr empty flag this bit is set to high whenever t he transmitter goes idle. it is set to low whenever either the thr or tsr contains a data character. in the fifo mode this bit is set to high whenever the transmit fifo and transmit shift register are both empty. lsr[7]: receive fifo data error flag ? logic 0 = no fifo error (default). ? logic 1 = a global indicator for the sum of all error bits in the rx fifo. at least one parity error, framing error or break indication is in the fifo data. this bit clears when there is no more error(s) in any of the bytes in the rx fifo.
xr16v564/564d 35 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 4.9 modem status register (msr) - read/write this register is writeable but it is not recommended. the msr provi des the current state of the modem interface input signals. lower four bits of this register are used to indica te the changed information. these bits are set to a high whenever a signal from the modem changes state. these bits may be used for general purpose inputs when they are not used with modem signals. msr[0]: delta cts# input flag ? logic 0 = no change on cts# input (default). ? logic 1 = the cts# input has changed state since the la st time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[1]: delta dsr# input flag ? logic 0 = no change on dsr# input (default). ? logic 1 = the dsr# input has changed state since the last time it was monitored. a modem status interrupt will be generated if msr interrup t is enabled (ier bit-3). msr[2]: delta ri# input flag ? logic 0 = no change on ri# input (default). ? logic 1 = the ri# input has changed from low to high, ending of the ringing signal. a modem status interrupt will be ge nerated if msr in terrupt is enabled (ier bit-3). msr[3]: delta cd# input flag ? logic 0 = no change on cd# input (default). ? logic 1 = indicates that the cd# input has changed st ate since the last time it was monitored. a modem status interrupt will be generated if msr interrupt is enabled (ier bit-3). msr[4]: cts input status cts# pin may function as automatic hardware flow control signal input if it is enabled and selected by auto cts (efr bit-7). auto cts flow contro l allows starting and stopping of local data transmissions based on the modem cts# signal. a high on the cts# pin will stop uart transmitte r as soon as the current character has finished transmission, and a low will resume data trans mission. normally msr bit-4 bit is the compliment of the cts# input. however in the loopba ck mode, this bit is equivalent to the rts# bit in the mcr register. the cts# input may be used as a general purpose input when the modem interface is not used. msr[5]: dsr input status normally this bit is the complement of the dsr# input. in the loopback mode, this bit is equivalent to the dtr# bit in the mcr register. the dsr# input may be used as a general purpose input when the modem interface is not used. msr[6]: ri input status normally this bit is the complement of the ri# input. in the loop back mode this bit is equivalent to bit-2 in the mcr register. the ri# input may be used as a general purpose input when the modem interface is not used. msr[7]: cd input status normally this bit is the complement of the cd# input. in the loopback mode this bit is equivalent to bit-3 in the mcr register. the cd# input may be used as a general purpose input when the modem interface is not used. 4.10 scratch pad register (spr) - read/write this is a 8-bit general purpose register for the user to store temporary data. the content of this register is preserved during sleep mode but becomes 0xff (default) after a reset or a power off-on cycle.
xr16v564/564d 36 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 4.11 baud rate generator registers (dll and dlm) - read/write these registers make-up the value of the baud rate divisor. the concatenation of the contents of dlm and dll gives the 16-bit divisor value. then the value is added to dld[3:0]/16 to achieve the fractional baud rate divisor. dld must be enabled via efr bit-4 before it can be accessed. see table 15 below and see ?section 2.8, programmable baud rate generator with fractional divisor? on page 13. dld[5:4]: sampli ng rate select these bits select the data sampling rate. by default, the data sampling rate is 16x. the maximum data rate will double if the 8x mode is selected and will quadruple if th e 4x mode is selected. see table 15 below. dld[7:6]: reserved 4.12 enhanced feature register (efr) - read/write enhanced features are enabled or disabled using this register. bit 0-3 provide si ngle or dual consecutive character software flow control selection (see table 16 ). when the xon1 and xon2 and xoff1 and xoff2 modes are selected, the double 8-bit words are concatenated in to two sequential characters. caution: note that whenever changing the tx or rx flow control bits, always reset all bits back to logic 0 (disable) before programming a new setting. efr[3:0]: software flow control select single character and dual sequential characters software flow control is supported. combinations of software flow control can be selected by programming these bits. t able 15: s ampling r ate s elect dld[5] dld[4] s ampling r ate 0 0 16x 0 1 8x 1 x 4x
xr16v564/564d 37 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo efr[4]: enhanced function bits enable enhanced function control bit. this bit enables ier bits 4- 7, isr bits 4-5, fcr bits 4-5, mcr bits 5-7, and dld to be modified. after modifying any enhanced bits, efr bi t-4 can be set to a low to latch the new values. this feature prevents legacy software from altering or over writing the enhanced functions once set. normally, it is recommended to leave it enabled, high. ? logic 0 = modification disable/latch enhanced features. ie r bits 4-7, isr bits 4-5, fcr bits 4-5, mcr bits 5- 7, and dld are saved to retain the user settings. after a reset, the ier bits 4-7, is r bits 4-5, fcr bits 4-5, and mcr bits 5-7, and dld are set to a low to be compatible with st16c550 mode (default). ? logic 1 = enables the above-mentioned register bits to be modified by the user. efr[5]: special character detect enable ? logic 0 = special character detect disabled (default). ? logic 1 = special character detect enabled. the ua rt compares each incomi ng receive character with data in xoff-2 register. if a match exists, the receive data will be transfer red to fifo and isr bit-4 will be set to indicate detection of the special character. bit-0 co rresponds with the lsb bit of the receive character. if flow control is set for comparing xon1, xo ff1 (efr [1:0]= ?10?) then flow control and special character work normally. however, if flow control is set for comparing xon2, xoff2 (efr[1:0]= ?01?) then flow control works normally, but xoff2 will not go to the fifo, and will ge nerate an xoff interrupt and a special character interrupt, if enabled via ier bit-5. t able 16: s oftware f low c ontrol f unctions efr bit -3 c ont -3 efr bit -2 c ont -2 efr bit -1 c ont -1 efr bit -0 c ont -0 t ransmit and r eceive s oftware f low c ontrol 0 0 0 0 no tx and rx flow control (default and reset) 0 0 x x no transmit flow control 1 0 x x transmit xon1, xoff1 0 1 x x transmit xon2, xoff2 1 1 x x transmit xon1 and xon2, xoff1 and xoff2 x x 0 0 no receive flow control x x 1 0 receiver compares xon1, xoff1 x x 0 1 receiver compares xon2, xoff2 1 0 1 1 transmit xon1, xoff1 receiver compares xon1 or xon2, xoff1 or xoff2 0 1 1 1 transmit xon2, xoff2 receiver compares xon1 or xon2, xoff1 or xoff2 1 1 1 1 transmit xon1 and xon2, xoff1 and xoff2, receiver compares xon1 and xon2, xoff1 and xoff2 0 0 1 1 no transmit flow control, receiver compares xon1 and xon2, xoff1 and xoff2
xr16v564/564d 38 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 efr[6]: auto rts flow control enable rts# output may be used for hardware flow control by setting efr bit-6 to logic 1. when auto rts is selected, an interrupt will be generated when the receive fifo is filled to the pr ogrammed trigge r level and rts de-asserts high at the next upper trigger level/hysteresis level. rts# will return low when fifo data falls below the next lower trigger leve l/hysteresis level. the rts# output must be asserted (low) before the auto rts can take effect. rts# pin will function as a general purpose ou tput when hardware flow control is disabled. ? logic 0 = automatic rts flow control is disabled (default). ? logic 1 = enable automatic rts flow control. efr[7]: auto cts flow control enable automatic cts flow control. ? logic 0 = automatic cts flow control is disabled (default). ? logic 1 = enable automatic cts flow control. data tr ansmission stops when cts# input de-asserts to logic 1. data transmission resumes when cts# returns to a low. 4.13 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write these registers are used as the prog rammable software flow control characters xoff1, xoff2, xon1, and xon2. for more details, see table 8 .
xr16v564/564d 39 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo t able 17: uart reset condit ions for channels a-d registers reset state dlm, dll dlm = 0x00 and dll = 0x01. only resets to these val - ues during a power up. they do not reset when the reset pin is asserted. dld bits 7-0 = 0x00 rhr bits 7-0 = 0xxx thr bits 7-0 = 0xxx ier bits 7-0 = 0x00 fcr bits 7-0 = 0x00 isr bits 7-0 = 0x01 lcr bits 7-0 = 0x00 mcr bits 7-0 = 0x00 lsr bits 7-0 = 0x60 msr bits 3-0 = logic 0 bits 7-4 = logic levels of the inputs inverted spr bits 7-0 = 0xff efr bits 7-0 = 0x00 xon1 bits 7-0 = 0x00 xon2 bits 7-0 = 0x00 xoff1 bits 7-0 = 0x00 xoff2 bits 7-0 = 0x00 i/o signals reset state tx high rts# high dtr# high rxrdy# high txrdy# low int (16 mode) xr16v564 = three-state condition (intsel = low) xr16v564 = low (intsel = high) xr16v564d = low irq# (68 mode) three-state condition (intsel = low)
xr16v564/564d 40 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 test 1: the following inputs remain steady at vcc or gnd stat e to minimize sleep current: a0-a2, d0-d7, ior#, iow#, csa#, csb#, csc#, and csd#. also, rxa, rxb, rxc, and rxd inputs must idle at high while asleep. absolute maximum ratings power supply range 4 volts voltage at any pin gnd-0.3 v to 4 v operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c package dissipation 500 mw typical package thermal resistance data (margin of error: 15%) thermal resistance (48-qfn) theta-ja = 28 o c/w, theta-jc = 10.5 o c/w thermal resistance (64-lqfp) theta-ja = 49 o c/w, theta-jc = 10 o c/w thermal resistance (68-plcc) theta-ja = 39 o c/w, theta-jc = 17 o c/w thermal resistance (80-lqfp) theta-ja = 37 o c/w, theta-jc = 7 o c/w electrical characteristics dc electrical characteristics u nless otherwise noted : ta = -40 o to +85 o c, v cc is 2.25 to 3.6v s ymbol p arameter l imits 2.5v m in m ax l imits 3.3v m in m ax u nits c onditions v ilck clock input low level -0.3 0.2 -0.3 0.6 v v ihck clock input high level 2.0 vcc 2.4 vcc v v il input low voltage -0.3 0.6 -0.3 0.8 v v ih input high voltage 2.0 5.5 2.2 5.5 v v ol output low voltage 0.4 v i ol = 4 ma 0.4 v i ol = 2 ma v oh output high voltage 2.0 v i oh = -1 ma 1.8 v i oh = -400 ua i il input low leakage current 15 15 ua i ih input high leakage current 15 15 ua c in input pin capacitance 5 5 pf i cc power supply current 1.7 3 ma ext clk = 2mhz i sleep sleep current 350 450 ua see test 1
xr16v564/564d 41 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo ac electrical characteristics ta = -40 o to +85 o c, v cc is 2.25 to 3.6v, 70 p f load where applicable s ymbol p arameter l imits 2.5v 10% m in m ax l imits 3.3v 10% m in m ax u nit xtal1 uart crystal frequency 24 24 mhz eclk external clock frequency 50 64 mhz t eclk external clock time period 10 7 ns t as address setup time (16 mode) 0 0 ns t ah address hold time (16 mode) 0 0 ns t cs chip select width (16 mode) 50 40 ns t rd ior# strobe width (16 mode) 50 40 ns t dy read cycle delay (16 mode) 50 40 ns t rdv data access time (16 mode) 45 35 ns t dd data disable time (16 mode) 10 10 ns t wr iow# strobe width (16 mode) 50 40 ns t dy write cycle delay (16 mode) 50 40 ns t ds data setup ti me (16 mode) 15 15 ns t dh data hold time (16 mode) 5 5 ns t ads address setup (68 mode) 0 0 ns t adh address hold (68 mode) 0 0 ns t rws r/w# setup to cs# (68 mode) 0 0 ns t rda data access time (68 mode) 45 35 ns t rdh data disable time (68 mode) 10 10 ns t wds write data setup (68 mode) 10 10 ns t wdh write data hold (68 mode) 5 5 ns t rwh cs# de-asserted to r/w# de-asserted (68 mode) 10 5 ns t csl cs# strobe width (68 mode) 50 40 ns t csd cs# cycle delay (68 mode) 50 40 ns t wdo delay from iow# to output 50 50 ns t mod delay to set interrupt from modem input 50 50 ns t rsi delay to reset interrupt from ior# 50 50 ns
xr16v564/564d 42 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 t ssi delay from stop to set interrupt 1 1 bclk t rri delay from ior# to reset interrupt 45 45 ns t si delay from start to interrupt 45 45 ns t int delay from initial int reset to transmit start 8 24 8 24 bclk t wri delay from iow# to reset interrupt 45 45 ns t ssr delay from stop to set rxrdy# 1 1 bclk t rr delay from ior# to reset rxrdy# 45 45 ns t wt delay from iow# to set txrdy# 45 45 ns t srt delay from center of start to reset txrdy# 8 8 bclk t rst reset pulse width 40 40 ns bclk baud clock 16x or 8x or 4x of data rate hz f igure 14. c lock t iming ac electrical characteristics ta = -40 o to +85 o c, v cc is 2.25 to 3.6v, 70 p f load where applicable s ymbol p arameter l imits 2.5v 10% m in m ax l imits 3.3v 10% m in m ax u nit osc clk clk external clock
xr16v564/564d 43 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo f igure 15. m odem i nput /o utput t iming f or c hannels a-d f igure 16. 16 m ode (i ntel ) d ata b us r ead t iming for c hannels a-d io w # io w rts# dtr# cd# cts# dsr# in t io r # ri# t wdo t mod t mod t rsi t mod active active change of state change of state active active active change of state change of state change of state a ctive a ctive t as t dd t ah t rd t rdv t dy t dd t rdv t ah t as t cs valid address valid address valid data valid data a0-a7 cs# ior# d0-d7 rdtm t cs t rd
xr16v564/564d 44 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 f igure 17. 16 m ode (i ntel ) d ata b us w rite t iming for c hannels a-d f igure 18. 68 m ode (m otorola ) d ata b us r ead t iming for c hannels a-d 16write t as t dh t ah t wr t ds t dy t dh t ds t ah t as t cs valid address valid address valid data valid data a0-a7 cs# iow# d0-d7 t cs t wr 68read t ads t rdh t adh t csl t rda t csd t rws valid address valid address valid data a0-a7 cs# r/w# d0-d7 t rwh valid data
xr16v564/564d 45 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo f igure 19. 68 m ode (m otorola ) d ata b us w rite t iming for c hannels a-d f igure 20. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d 68write t ads t adh t csl t wds t csd t rws valid address valid address valid data a0-a7 cs# r/w# d0-d7 t rwh valid data t wdh rx rxrdy# ior# int d0:d7 start bit d0:d7 stop bit d0:d7 t ssr 1 byte in rhr active data ready active data ready active data ready 1 byte in rhr 1 byte in rhr t ssr t ssr rxnfm t rr t rr t rr t ssr t ssr t ssr (reading data out of rhr)
xr16v564/564d 46 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 f igure 21. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a-d tx txrdy# iow# int* d0:d7 start bit d0:d7 stop bit d0:d7 t wt txnonfifo t wt t wt t wri t wri t wri t srt t srt t srt *int is cleared when the isr is read or when data is loaded into the thr. isr is read isr is read isr is read (loading data into thr) (unloading) ier[1] enabled rx rxrdy# ior# int d0:d7 s t ssr rxintdma# rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties first byte is received in rx fifo d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo)
xr16v564/564d 47 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo f igure 23. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a-d f igure 24. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a-d rx rxrdy# ior# int d0:d7 s t ssr rxfifodma rx fifo fills up to rx trigger level or rx data timeout rx fifo drops below rx trigger level fifo empties d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t rr t rri t ssi (reading data out of rx fifo) tx txrdy# iow# int* txdma# d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level data in tx fifo tx fifo empty t wt t srt tx fifo empty t t s t si isr is read ier[1] enabled isr is read *int is cleared when the isr is read or when tx fifo fills up to the trigger level.
xr16v564/564d 48 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 f igure 25. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a-d tx txrdy# iow# int* d0:d7 s txdma d0:d7 s d0:d7 t d0:d7 s d0:d7 s t d0:d7 s t t d0:d7 s t start bit stop bit t wri t (unloading) (loading data into fifo) last data byte transmitted tx fifo fills up to trigger level tx fifo drops below trigger level at least 1 empty location in fifo t srt tx fifo full t wt t si isr read isr read *int cleared when the isr is read or when tx fifo fills up to trigger level. ier[1] enabled
xr16v564/564d 49 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo package dimensions 48 lead quad flat no lead (7 x 7 x 0.9 mm, 0.50 mm pitch qfn) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a3 0.006 0.010 0.15 0.25 d 0.270 0.281 6.85 7.15 d2 0.201 0.209 5.10 5.30 b 0.007 0.012 0.18 0.30 e 0.0197 bsc 0.50 bsc l 0.012 0.020 0.30 0.50 k 0.008 - 0.20 - note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm. the lead may be half-etched terminal.
xr16v564/564d 50 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 64 lead low-profile quad flat pack (10 x 10 x 1.4 mm lqfp) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.465 0.480 11.80 12.20 d1 0.390 0.398 9.90 10.10 e 0.020 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 0 7 0 7 48 33 32 17 116 49 64 d d 1 d d 1 b e a 2 a 1 a seating plane l c
xr16v564/564d 51 rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 68 lead plastic leaded chip carrier (plcc) note: the control dimension is the inch column inches millimeters symbol min max min max a 0.165 0.200 4.19 5.08 a 1 0.090 0.130 2.29 3.30 a 2 0.020 ---. 0.51 --- b 0.013 0.021 0.33 0.53 b 1 0.026 0.032 0.66 0.81 c 0.008 0.013 0.19 0.32 d 0.985 0.995 25.02 25.27 d 1 0.950 0.958 24.13 24.33 d 2 0.890 0.930 22.61 23.62 d 3 0.800 typ. 20.32 typ. e 0.050 bsc 1.27 bsc h 1 0.042 0.056 1.07 1.42 h 2 0.042 0.048 1.07 1.22 r 0.025 0.045 0.64 1.14 1 d d 1 d d 1 d 3 d 2 a a 1 268 b a 2 b 1 e seating plane d 3 45 x h 2 45 x h 1 c r
xr16v564/564d 52 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 80 lead plastic quad flat pack (12 mm x 12 mm lqfp, 1.4 mm form) note: the control dimensio n is the millimeter column inches millimeters symbol min max min max a 0.055 0.063 1.40 1.60 a1 0.002 0.006 0.05 0.15 a2 0.053 0.057 1.35 1.45 b 0.007 0.011 0.17 0.27 c 0.004 0.008 0.09 0.20 d 0.543 0.559 13.80 14.20 d1 0.465 0.480 11.80 12.20 e 0.0197 bsc 0.50 bsc l 0.018 0.030 0.45 0.75 0 7 0 7 p
53 notice exar corporation reserves the right to make changes to the products contained in this publicat ion in order to improve design, performanc e or reliability. exar corp oration assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent in fringement. charts and sc hedules contained here in are only for illustration purposes and may vary depending upon a user?s specific application. while the information in this publication has been carefully ch ecked; no responsibility, however , is assumed for inaccuracies. exar corporation does not re commend the use of any of its products in life suppo rt applications where the failure or malfunction of the product can reasonably be ex pected to cause failure of the life support system or to significantly affect its safety or effectiveness. products ar e not authorized for use in such applications unless exar corporation receives , in writing, assurances to its satisfaction that: (a) the ri sk of injury or damage has been minimized; (b) the us er assumes all such risks; (c) potential liability of exar corporation is adequately protected under the circumstances. copyright 2007 exar corporation datasheet may 2007. reproduction, in part or whole, without the prior written consent of exar co rporation is prohibited. xr16v564/564d rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo revision history d ate r evision d escription september 2006 rev p1.0.0 preliminary datasheet. january 2007 rev 1.0.0 final datasheet. updated ac and dc electrical characteristics. may 2007 rev 1.0.1 updated qfn package dimensions drawing to show minimum "k" parameter. delete blank page.
xr16v564/564d i 2.25v to 3.6v quad uart with 32-byte fifo rev. 1.0.1 table of contents general description ......... ................ ................ ................. .............. .............. .......... 1 f eatures ............................................................................................................................... ..................... 1 a pplications ............................................................................................................................... ................ 1 f igure 1. xr16v564 b lock d iagram ............................................................................................................................... ............ 1 f igure 2. p in o ut a ssignment f or 68- pin plcc p ackages i n 16 and 68 m ode and 64- pin lqfp p ackages .......................... 2 f igure 3. p in o ut a ssignment f or 48- pin qfn p ackage and 80- pin lqfp p ackage ............................................................... 3 pin descriptions ............ ................ ................. ................ ................. ................ .......... 4 ordering information ............................................................................................................................... . 4 1.0 product description........................................................................................................ ............... 9 2.0 functional descriptions.................................................................................................... ......... 10 2.1 cpu interface.............................................................................................................. ................................. 10 f igure 4. xr16v564 t ypical i ntel /m otorola d ata b us i nterconnections ........................................................................... 10 2.2 device reset .... .............. .............. .............. .............. .............. .............. .............. ......... .................................. 11 2.3 channel selection........... .............. .............. .............. .............. .............. .............. ........... ........................... 11 t able 1: c hannel a-d s elect in 16 m ode .............................................................................................................................. ... 11 t able 2: c hannel a-d s elect in 68 m ode .............................................................................................................................. ... 11 2.4 channels a-d internal registers . .............. .............. .............. .............. .............. ........... .......... ........... 12 2.5 int ouputs for channels a-d ... .............. .............. .............. .............. .............. .............. ......... ................. 12 t able 3: int p in o peration for t ransmitter for c hannels a-d ........................................................................................... 12 t able 4: int p in o peration for r eceiver for c hannels a-d ................................................................................................. 12 2.6 dma mode................................................................................................................... ..................................... 12 t able 5: txrdy# and rxrdy# o utputs in fifo and dma m ode for c hannels a-d ........................................................... 13 2.7 crystal oscillator or external clock input .......... .............. .............. ........... ........... ........... ....... 13 f igure 5. t ypical c rystal c onnections ............................................................................................................................... .... 13 2.8 programmable baud rate generator with fractional divisor............................................ 13 f igure 6. b aud r ate g enerator ............................................................................................................................... ................ 14 t able 6: t ypical data rates with a 24 mh z crystal or external clock at 16x s ampling ................................................... 15 2.9 transmitter ................................................................................................................ .................................. 15 2.9.1 transmit holding register (thr) - write only ............................................................................. .............. 15 2.9.2 transmitter operation in non-fifo mode ................................................................................... ................. 16 f igure 7. t ransmitter o peration in non -fifo m ode .............................................................................................................. 16 2.9.3 transmitter operation in fifo mode ....................................................................................... ...................... 16 f igure 8. t ransmitter o peration in fifo and f low c ontrol m ode ..................................................................................... 16 2.10 receiver .................................................................................................................. ..................................... 17 2.10.1 receive holding register (rhr) - read-only .............................................................................. .............. 17 f igure 9. r eceiver o peration in non -fifo m ode .................................................................................................................... 17 f igure 10. r eceiver o peration in fifo and a uto rts f low c ontrol m ode ....................................................................... 18 2.11 auto rts (hardware) flow control .......................................................................................... ...... 18 2.12 auto rts hysteresis....................................................................................................... ......................... 18 t able 7: a uto rts (h ardware ) f low c ontrol ........................................................................................................................ 18 2.13 auto cts flow control ..................................................................................................... .................... 19 f igure 11. a uto rts and cts f low c ontrol o peration ....................................................................................................... 19 2.14 auto xon/xoff (software) flow control..................................................................................... . 20 t able 8: a uto x on /x off (s oftware ) f low c ontrol ............................................................................................................... 20 2.15 special character detect ...... .............. .............. .............. .............. .............. ............ ......... ................. 20 2.16 infrared mode ............................................................................................................. .............................. 21 f igure 12. i nfrared t ransmit d ata e ncoding and r eceive d ata d ecoding .......................................................................... 21 2.17 sleep mode with auto wake-up.. .............. .............. .............. .............. .............. ........... ........... ............. 22 2.18 internal loopback ..... .............. .............. .............. .............. ........... ........... ........... .......... ......................... 22 f igure 13. i nternal l oop b ack in c hannel a and b ................................................................................................................ 23 3.0 uart internal registers .................................................................................................... ......... 24 t able 9: uart channel a and b uart internal registers ............................................................................ .......... 24 t able 10: internal registers description. s haded bits are enabled when efr b it -4=1 ....................................... 25 4.0 internal register descriptions............................................................................................. .. 26 4.1 receive holding register (rhr) - read- only ........... .............. .............. .............. .............. ............. .. 26 4.2 transmit holding register (thr) - write-only ............................................................................... 26 4.3 interrupt enable register (ier) - read/write.......... .............. .............. .............. .............. ............. .. 26 4.3.1 ier versus receive fifo interrupt mode operation ......................................................................... ...... 26 4.3.2 ier versus receive/transmit fifo polled mode operation .................................................................. 27
xr16v564/564d ii rev. 1.0.1 2.25v to 3.6v quad uart with 32-byte fifo 4.4 interrupt status register (isr) - read-only ......... .............. .............. .............. ............... .............. .. 28 4.4.1 interrupt generation: .................................................................................................... .................................... 28 4.4.2 interrupt clearing: ...................................................................................................... ....................................... 28 t able 11: i nterrupt s ource and p riority l evel ..................................................................................................................... 29 4.5 fifo control register (fcr) - write-only ................................................................................... ..... 29 t able 12: t ransmit and r eceive fifo t rigger l evel s election ............................................................................................ 30 4.6 line control register (lcr) - read/write ................................................................................... ..... 31 t able 13: p arity selection .............................................................................................................................. .......................... 32 4.7 modem control register (m cr) or general purpose outp uts control - read/write . 32 t able 14: int o utput m odes .............................................................................................................................. ....................... 33 4.8 line status register (lsr) - read/write .................................................................................... ........ 34 4.9 modem status register (msr) - read/write................................................................................... ... 35 4.10 scratch pad register (spr) - re ad/write .............. .............. .............. .............. ............... ............ .... 35 4.11 baud rate generator registers (dll and dlm) - read/write.......... ........... ............ ........... ..... 36 t able 15: s ampling r ate s elect .............................................................................................................................. ................. 36 4.12 enhanced feature register (efr) - read/write ........... .............. .............. .............. .............. ........ 36 t able 16: s oftware f low c ontrol f unctions ........................................................................................................................ 37 4.13 software flow control registers (xoff1, xoff2, xon1, xon2) - read/write................... 38 t able 17: uart reset conditions for channels a-d ................................................................................... .............. 39 absolute maximum ratings ......... ................. ................ .............. .............. ........... 40 typical package thermal resistance data (margin of error: 15%) 40 electrical characteristics....... ................. ................ .............. .............. ........... 40 dc e lectrical c haracteristics ............................................................................................................. 40 ac e lectrical c haracteristics ............................................................................................................. 41 ta = -40 o to +85 o c, v cc is 2.25 to 3.6v, 70 p f load where applicable ............................................. 41 f igure 14. c lock t iming ............................................................................................................................... .............................. 42 f igure 15. m odem i nput /o utput t iming f or c hannels a-d .................................................................................................... 43 f igure 16. 16 m ode (i ntel ) d ata b us r ead t iming for c hannels a-d ................................................................................... 43 f igure 17. 16 m ode (i ntel ) d ata b us w rite t iming for c hannels a-d .................................................................................. 44 f igure 18. 68 m ode (m otorola ) d ata b us r ead t iming for c hannels a-d........................................................................... 44 f igure 20. r eceive r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d ............................................................ 45 f igure 19. 68 m ode (m otorola ) d ata b us w rite t iming for c hannels a-d ......................................................................... 45 f igure 21. t ransmit r eady & i nterrupt t iming [n on -fifo m ode ] for c hannels a-d .......................................................... 46 f igure 22. r eceive r eady & i nterrupt t iming [fifo m ode , dma d isabled ] for c hannels a-d........................................... 46 f igure 23. r eceive r eady & i nterrupt t iming [fifo m ode , dma e nabled ] for c hannels a-d............................................ 47 f igure 24. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode d isabled ] for c hannels a-d .............................. 47 f igure 25. t ransmit r eady & i nterrupt t iming [fifo m ode , dma m ode e nabled ] for c hannels a-d ............................... 48 p ackage d imensions ............................................................................................................................... . 49 r evision h istory ............................................................................................................................... ...... 53 table of contents .......... ................ ................. ................ .............. .............. .............. i

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